8-Stage Verification — AI Proposes, a Deterministic Verifier Decides

Passing simulation ≠ safe for production. This is exactly how breadboards used to betray beginners — by letting one kind of success be mistaken for total success. That is why ibouPCB splits verification into three gates and never displays them mixed together.

The three verification gates

Gate	What it verifies	What it cannot verify	Tool
① Logic verification	Does the code run as intended	All electrical safety	Simulator (L0)
② Electrical verification	Will it not burn out	Real-world noise · EMI	ERC + DRC engines
③ Physical verification	Does it actually work	—	You, in person

Both ① and ② must be green before the download buttons open.
③ never turns green automatically. You check it yourself after receiving the board and confirming it in person.
What the simulator cannot catch is always stated explicitly: power-supply noise, ground bounce, EMI, sensor timing variation, component tolerances.

AI only proposes; the verdict is deterministic

Circuit expansion has two proposal sources. One is the deterministic expander, which builds a netlist from rules and the catalog's reference circuits; the other is the AI proposer (N=3 samples) constrained by a JSON schema. Whichever produced it, a proposal is adopted only if it passes every verifier below. There is no AI in the verifier code — it is all deterministic code.

The AI cannot invent parts outside the catalog. Proposals specify parts by catalog ID only, and any ID that does not exist is rejected immediately.
If any single stage produces an error, the proposal is not adopted. Warnings are shown to the user and the process continues.
If no AI key is configured or consensus fails, it always falls back to the deterministic expander.
Every verdict leaves its evidence. Each golden pattern records its source (the official Arduino schematic, the Espressif hardware design guidelines, and so on).

The 8 stages (P1–P8)

Stage	Check	What it prevents
P1 Schema	Are the part · net · pin structures well-formed	Broken proposals
P2 Catalog grounding	Does every part ID and pin name actually exist in the catalog	AI hallucinations (nonexistent parts · pins)
P3 Golden patterns	Is the required support circuitry present for each MCU · regulator · interface	"Silent" failures such as a missing EN pull-up or missing decoupling
P4 ERC rules	Voltage domains, I²C address conflicts, pull-ups, current budget, flyback, boot-strapping pins…	The things beginners actually burn out
P5 Pin Contract	Is every logical pin in the .ino mapped 1:1, with matching PWM · interrupt · ADC capability	A board that differs from the code
P6 Consensus (AI only)	Compare the normalized net topology of N samples; discard if there is no majority agreement	Proposals that passed by accident
P7 KiCad DRC	Board generation → Freerouting routing → kicad-cli pcb drc	Unmanufacturable boards (clearance · track width · drill)
P8 Simulation regression	Compare pre- and post-conversion simulation records against the Pin Contract	"The board is right but the code runs differently"

P1–P6 run without KiCad and finish within seconds. P7 runs as a separate process in a KiCad 9 container (GPL tools are never linked or bundled), and P8 is carried out jointly by the browser simulator and the server.

Golden patterns — facts read from real open-source circuits

The data behind P3 is not rules someone made up; it is patterns read from published schematics.

Target	Pattern	Source
ESP32-WROOM-32	EN 10 kΩ pull-up + 0.1 µF, 10 µF + 0.1 µF decoupling on 3V3	Espressif Hardware Design Guidelines, Adafruit HUZZAH32, four Olimex ESP32 boards
ATmega328P	16 MHz crystal + 22 pF × 2, RESET 10 kΩ pull-up, VCC / AVCC 100 nF	Official Arduino Uno Rev3 schematic
AMS1117-3.3	10 µF input, 10 µF output (+100 nF)	Datasheet recommended circuit
Relay coil	NPN driver + base resistor + flyback diode	Arduino relay module circuit
I²C bus	Exactly one set of SDA / SCL pull-ups (2.2 k–10 k)	NXP I²C specification
DS18B20	DQ 4.7 kΩ pull-up	Maxim datasheet

Patterns are corrected by checking them against real boards. For example, when four Olimex ESP32 boards were imported, the EN pull-up and 3V3 bulk capacitor matched the hand-written pattern, but none of the four boards had an external IO0 pull-up (button + internal pull-up instead). So the severity of the IO0 pull-up was adjusted from error to warning. The verifier changes only when there is evidence like this.

P4 ERC rules — the things that actually burn out

Voltage domain mismatch — 3.3 V GPIO ↔ 5 V sensor wired directly → level shifter / voltage divider auto-inserted
GPIO current exceeded — per pin · per port total · whole chip → driver transistor proposed
I²C address conflict — two identical addresses on the same bus (e.g. 0x68 MPU6050 + DS3231) → module with a changeable address proposed
I²C pull-up missing / duplicated — total pull-up per bus → auto-calculated · inserted
Power budget exceeded — regulator rating vs. total load → higher-rated regulator proposed
Inductive load unprotected — relay · motor · solenoid → flyback diode inserted
Decoupling missing — 0.1 µF per IC power pin → auto-inserted
Non-PWM / non-interrupt pin used for PWM / interrupts, duplicate pin assignment → reassignment proposed
Boot-strapping pin misuse — ESP32 GPIO0 / 2 / 12 / 15 → warning + reassignment
No reverse-polarity · ESD protection → diode / P-MOSFET, TVS proposed

What the result looks like

✅ P1 Schema                 passed
✅ P2 Catalog grounding      passed (all 14 parts exist in catalog)
✅ P3 Golden patterns        passed — ESP32-WROOM-32 EN pull-up·decoupling (Espressif HDG §2.1)
⚠️ P4 ERC                    1 warning — HC-SR04 ECHO 5V→3.3V: voltage divider auto-inserted
✅ P5 Pin Contract           passed — 5/5 logical pins mapped, 2 PWM requirements met
✅ P6 Consensus              3/3 sample topologies agree
✅ P7 KiCad DRC              0 violations (unconnected 0)
✅ P8 Simulation regression  6 pins compared, all match

It shows everything: which check, on what evidence, fixed what. Because this is an educational product. And beneath all of this green there is always "⚠️ Physical verification pending".